As AI training clusters scale from thousands of GPUs toward a million, what truly chokes compute is often not the GPU itself but the invisible pipelines that link GPUs together. Over the past two years, market attention has centered on advanced process nodes, HBM, and advanced packaging; now, high-speed interconnect is becoming the next major battleground in the race for AI compute. For US investors, this track features not only system-level giants like NVIDIA but also a growing group of niche pick-and-shovel players.
Why Interconnect Has Become the New Bottleneck of AI Compute
The essence of large-model training is welding thousands upon thousands of GPUs into one supercomputer. Compute scaling has long shifted from stacking single chips to stacking clusters, and cluster efficiency depends heavily on the communication speed between chips. The industry commonly uses Model FLOPs Utilization (MFU) to measure a cluster's true efficiency—even with top-tier GPUs in hand, if the interconnect can't keep up, massive compute is wasted waiting for data, and actual utilization may fall far short.
This is the logical starting point for revaluing high-speed interconnect. As widely observed in the industry, in clusters of ten thousand GPUs or more, communication overhead increasingly weighs on training efficiency; on the inference side, as Mixture-of-Experts (MoE) architectures and long contexts go mainstream, cross-node bandwidth demand is rising in step. In other words, the stronger the GPUs and the bigger the cluster, the more the interconnect matters—a textbook weakest-link market.
The Three-Way Battle Among Technology Routes
Camp NVLink: NVIDIA's Moat
NVIDIA's NVLink has long been the benchmark for proprietary interconnect, with bandwidth far beyond traditional PCIe; paired with NVSwitch, it can organize large numbers of GPUs into one logical giant GPU. Even more notable is the opening of NVLink Fusion—NVIDIA has begun allowing third-party CPUs and custom ASICs to plug into the NVLink ecosystem. That means interconnect is evolving from an in-house technology into a platform business, further widening the moat.
Camp Ethernet: The Open-Standards Counterattack
Hyperscale cloud providers are unwilling to be locked into a single ecosystem. The open-standards camp, represented by the Ultra Ethernet Consortium, is trying to let mature Ethernet technology handle the ultra-low latency and lossless transmission AI training requires; Broadcom's Tomahawk switch chip family and NVIDIA's own Spectrum-X Ethernet are both vying for say over the AI back-end network. For cloud providers, open standards mean bargaining power and supply-chain diversification—the commercial momentum behind this route is more than sufficient.
CPO and Optical Interconnect: The Ultimate Evolution of the Physical Layer
When the reach and power draw of electrical signals over copper approach their limits, optical interconnect becomes the inevitable choice. Co-Packaged Optics (CPO) packages the optical engine together with the switch chip, sharply cutting power and latency; transitional schemes such as Linear Pluggable Optics (LPO) are also spreading fast. As 800G and even 1.6T optical modules ramp up in AI data centers and per-lane speeds keep climbing, the optical interconnect supply chain is entering a window of rising volume and price.
A US Stock Roadmap: Who Is Selling the Shovels
The high-speed interconnect value chain can be split into four segments, each with corresponding US-listed plays:
- Switch chips and integrated platforms: Broadcom is one of the biggest players in AI networking chips, with the Tomahawk and Jericho families covering multiple tiers from in-rack to cluster level; NVIDIA, meanwhile, builds a full-stack solution of NVLink plus NVSwitch plus Spectrum-X, binding interconnect deeply into the CUDA ecosystem.
- Interconnect chips and retimers: Astera Labs focuses on PCIe and CXL retimers and smart interconnect modules, positioned at connection nodes inside servers and between racks; Credo is growing rapidly in high-speed SerDes and active electrical cables (AEC); Marvell is betting on interconnect DSPs, optical DSPs, and custom switch chips all at once, offering ample upside.
- Optical modules and components: US-listed optical component makers such as Coherent and Lumentum benefit from the upgrade cycle from 800G to 1.6T; the high-beta plays in optical module assembly are mostly Chinese ADRs listed overseas, but the US-listed value in upstream chips and components is equally hard to ignore.
- Network equipment and system integration: Arista Networks, with its deep ties to cloud giants and the white-box market, is a direct beneficiary of the AI back-end network; Cisco is also accelerating its pivot to AI networking in search of a second growth curve.
Notably, the interconnect business generally behaves like a consumable—the larger the cluster and the faster the iteration, the more sustained the demand for replacing and expanding interconnect components. This complements the strong generation-by-generation cycle of GPUs and helps smooth earnings volatility for the companies involved.
Risks and Timing: What Investors Should Watch
First, the battle over technology routes carries uncertainty. CPO's direction is clear, but yield, maintenance, and ecosystem adaptation still need time to ramp; if penetration lags expectations, valuations of related names could come under pressure. Second, high customer concentration is an industry-wide issue—once hyperscalers' capex pace slows, order swings along the interconnect chain get amplified in both directions. Third, the competitive landscape is shifting fast: boundaries among NVIDIA, Broadcom, Marvell, and startups are blurring, and shifting share could reshape the valuation framework at any time.
For ordinary investors, rather than chasing news of one-off breakouts, it is better to track three indicators: first, the capex guidance in cloud providers' earnings reports—the master valve of interconnect demand; second, the pace of speed upgrades in switch chips and optical modules, since generational transitions often deliver outsized profits; third, the rollout progress of standards bodies such as the Ultra Ethernet Consortium and UALink, as every step forward for open ecosystems can shift the balance of power among camps.
Standing in the second half of the compute race, the arms race over chip performance is migrating toward system-level efficiency, and high-speed interconnect is the central link of that migration. It lacks the star power of GPUs, yet it determines how much real output every dollar of compute investment can deliver. For US investors, this invisible track may well be the richest vein worth digging deep in the next phase of the AI market.
